1. Field of the Invention
The invention generally relates to image sensor systems; and in particular, the present invention relates to an image sensor utilizing a digital pixel sensor architecture.
2. Background of the Invention
Digital photography is one of the most exciting technologies that have emerged in the past years. With the appropriate hardware and software (and a little knowledge), anyone can put the principles of digital photography to work. Digital cameras, for example, are on the cutting edge of digital photography. Recent product introductions, technological advancements, and price cuts, along with the emergence of email and the World Wide Web, have helped make digital cameras the hottest new category of consumer electronics products.
Digital cameras, however, do not work in the way that traditional film cameras do. In fact, they are more closely related to computer scanners, copiers, or fax machines. Most digital cameras use an image sensor or photosensitive device, such as charged-coupled device (CCD) or Complementary Metal-Oxide Semiconductor (CMOS) to sense a scene. The photosensitive device reacts to light reflected from the scene and can translate the strength of that reaction into electronic charging signals that are further digitized. By passing light through red, green, and blue filters, for example, the reaction can be gauged for each separate color spectrum. When the readings are combined and evaluated via software, the camera can determine the specific color of each segment of the picture. Because the image is actually a collection of numeric data, it can easily be downloaded into a computer and manipulated for more artistic effects.
Digital cameras, however, do not have the resolution attainable with conventional photography. While traditional film-based technology, limited only by the granularity of the chemically based film, typically has a resolution of tens of millions of pixels, image sensors for use in most commercially available digital cameras acceptable to general consumers have a resolution of slightly more than one or two million pixels. Although digital cameras having resolutions of up to six million pixels are available, these high-resolution cameras are prohibitively expensive. Furthermore, the dynamic range of digital image sensors is often not as broad as is capable with film-based conventional photography. This is especially true for CMOS image sensors which, in general, have lower dynamic ranges than CCDs.
U.S. Pat. No. 5,461,425 to B. Fowler et al. describes a CMOS image sensor with pixel level analog-to-digital conversion. Such an image sensor, referred to as a digital pixel sensor (DPS), provides a digital output signal at each pixel element representing the light intensity detected by that pixel element. The combination of a phototransistor and an analog-to-digital (A/D) converter helps enhance detection accuracy and reduce power consumption, and improves overall system performance. Furthermore, U.S. patent application Ser. No. 09/567,638 describes an integrated DPS sensor with an on-chip memory for storing at least a frame of the image data. The incorporation of an on-chip memory alleviates the data transmission bottleneck problem associated with the use of an off-chip memory for storage of the pixel data. In particular, the integration of a memory with a DPS sensor makes feasible the use of multiple sampling for improving the quality of the captured images. Multiple sampling is recognized as the technique capable of achieving a wide dynamic range without many of the disadvantages associated with other dynamic range enhancement techniques, such as degradation in signal-to-noise ratio and increased implementation complexity. U.S. patent application Ser. No. 09/567,786 describes a method for facilitating image multiple sampling using a time-indexed approach. The aforementioned patent and patent applications are incorporated herein by reference in their entireties.
In the DPS sensor of the ""425 patent, the analog-to-digital conversion (ADC) is based on first order sigma delta modulation. While this ADC approach requires fairly simple and robust circuits, it has the disadvantages of producing too much data and suffering from poor low light performance. U.S. Pat. No. 5,801,657, and U.S. patent application Ser. No. 09/274,202 provide alternative ADC mechanisms that can significantly improve the overall system performance while minimizing the size of the A/D converters. The aforementioned patent and patent application are incorporated herein by reference in their entireties.
What is needed is a digital image sensor with integrated supporting circuitry for improving the performance of the image sensor.
In accordance with one aspect of the present invention, an image sensor includes a sensor array, a data memory and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement. The data memory is in communication with the sensor array and stores the pixel data. The pixel normalization circuit is coupled to the data memory for rearranging the pixel data into a pixel-bit order and providing the rearranged pixel data as output signals.
In accordance with another aspect of the present invention, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The data memory is in communication with the sensor array for storing the pixel data. The pixel normalization circuit is coupled to the data memory for normalizing the pixel data and providing normalized pixel data as output signals. In one embodiment, the sensor array outputs the pixel data in a sensor-bit arrangement and the pixel normalization circuit includes a pixel rearrangement circuit for rearranging the pixel data into a pixel-bit arrangement. In another embodiment, the sensor array outputs the pixel data represented in Gray code and the pixel normalization circuit includes a conversion circuit for converting the pixel data into a binary representation. In another embodiment, the data memory stores reset values for each of the pixel elements in the sensor array and the pixel normalization circuit includes a reset subtract circuit for subtracting the reset values from the pixel data for each of the pixel elements. In yet another embodiment, the sensor array uses multiple sampling for establishing a wide dynamic range for the sensor array, and the data memory includes a time index memory for storing the time index value for each of the pixel elements. In another embodiment, the pixel normalization circuit includes a multiple sampling normalization circuit for calculating the normalized pixel data for each of the pixel elements based on the pixel data and the time index values.
According to another aspect of the present invention, a method for constructing an n-bit Gray code to binary conversion circuit is described. A method for converting an n-bit Gray code number to an n-bit binary number includes (1) computing the binary value of the least significant bit (LSB) of the n-bit Gray code number using an XOR tree; the XOR tree including a first set of XOR gates for evaluating the n-bit Gray code number and generating the binary value of the LSB in a shortest gate delay time; (2) determining in the XOR tree a first group of bits, other than the LSB, for which binary values of the first group of bits are also generated; and (3) providing a second set of XOR gates for computing the binary values of a second group of bits of the n-bit Gray code number, other than the first group of bits and the LSB, the second set of XOR gates computing the binary values in a gate delay time less than or equal to the shortest gate delay time of the XOR tree.
According to yet another aspect of the present invention, a method for converting an n-bit Gray code number to an n-bit binary number includes: (1) providing a plurality of building blocks for converting 2-bit, 3-bit, and 4-bit Gray code numbers, each of said building blocks including one or more XOR gates and having the shortest gate delay time for converting a 2-bit, 3-bit or 4-bit Gray code number; (2) selecting a combination of said building blocks for converting said n-bit Gray code number; and (3) providing a first set of XOR gates at output terminals of said building blocks for converting the lower order bits, as necessary, of said n-bit Gray code number. The Gray code to binary conversion circuits according to the present invention provides high speed conversion and conserves circuit area.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.